The present invention relates to a method of configuring a plurality of configurable math hardware accelerators of an integrated microprocessor circuit via a configuration controller and a corresponding microprocessor circuit comprising the configuration controller. The configuration controller may be operating as interface between a Digital Signal Processor (DSP) core or a microprocessor core and the plurality of configurable math hardware accelerators. The latter accelerators or computing units are specialized mathematical hardware computational units configured to compute certain types of signal processing functions that involve arithmetic or mathematical calculations. The mathematical calculations are typically associated with complex numerical computations of advanced digital signal processing algorithms. Exemplary signal processing functions include FFT, iFFT, vector*matrix multiplications, FIR/IIR filter multiplications, logarithms, square roots, etc. Existing math hardware accelerators are often interfaced to a microprocessor core by memory mapping into a main data memory of the microprocessor circuit or alternatively interfaced to one or more I/O ports of the microprocessor circuit. For a large number of microprocessor circuits and associated systems these prior art interface methodologies to the math hardware accelerators are unsatisfactory solutions because of computational overhead of maintaining a memory mapped or I/O port model. This computational overhead and power overhead is incurred to the DSP or microprocessor core by continuously updating content of the respective configuration registers of the math hardware accelerator(s). On the other hand, it is highly desirable to provide each math hardware accelerator with a relatively flexible structure or topology via numerous programmable parameters and corresponding configuration registers such that functionality can be tailored to requirements of a specific type of signal processing application. The ability to tailor the functionality of the math hardware accelerator to specific applications allows use or re-use of the math hardware accelerator in a broad range of applications such that individual demands from a diversified customer base can be served.
U.S. Pat. No. 6,256,724 B1 discloses a microprocessor with a DSP core and a re-configurable hardware coprocessor. The re-configurable hardware co-processor may be adapted to calculate various mathematical functions based on a set of functional units like multipliers and adders. The DSP core loads data and coefficients to be used by the re-configurable hardware coprocessor into a data memory and coefficient memory, respectively. This loading of data may be performed directly by the DSP core or performed indirectly via control of a DMA circuit. The data memory and coefficient memory are coupled to a common data bus used by the DSP core and the hardware coprocessor. The DSP core sends a command to the hardware co-processor about selection of a desired signal processing algorithm via a command to the command memory of the hardware coprocessor.
“INTERFACE DESIGN APPROACH FOR SYSTEM ON CHIP BASED ON CONFIGURATION” ISCAS Paper, Issam MAALEJ et al. This paper discloses a communication interface between a RISC processor and a hardware accelerator mounted on a SOC chip. The hardware accelerator can be adapted for DCT, FIR etc. computations. The communication interface reads all data to be processed by the hardware accelerator from the RISC core. The data are written to the selected hardware accelerator when that latter is ready by start command issued by the communication interface. The communication interface reads the result of the hardware accelerator computations when ready and writes the results to the RISC core.
U.S. 2005/0027965 A1 discloses a microprocessor with a CPU, a Floating Point Unit (FPU) and a byte-code accelerator (BCA). The BCA translates intermediate byte code generated by JAVA into a native format of the microprocessor and FPU.